View IDT71V65702_2356418.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

october 2004 dsc-5315/08 1 ?2004 integrated device technology, inc. pin description summary features u u u u u 256k x 36, 512k x 18 memory configurations u u u u u supports high performance system speed - 100 mhz (7.5 ns clock-to-data access) u u u u u zbt tm feature - no dead cycles between write and read cycles u u u u u internally synchronized output buffer enable eliminates the need to control oe oe oe oe oe u u u u u single r/ w w w w w (read/write) control pin u u u u u 4-word burst capability (interleaved or linear) u u u u u individual byte write ( bw bw bw bw bw 1 - bw bw bw bw bw 4 ) control (may tie active) u u u u u three chip enables for simple depth expansion u u u u u 3.3v power supply (5%) u u u u u 2.5v (5%) i/o supply (v ddq ) u u u u u power down controlled by zz input u u u u u packaged in a jedec standard 100-pin plastic thin quad flatpack (tqfp), 119 ball grid array (bga) and 165 fine pitch ball grid array (fbga). description the IDT71V65702/5902 are 3.3v high-speed 9,437,184-bit (9 megabit) synchronous srams organized as 256k x 36 / 512k x 18. they are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. thus they have been given the name zbt tm , or zero bus turnaround. address and control signals are applied to the sram during one clock cycle, and on the next clock cycle the associated data cycle a 0 -a 18 address inputs input synchronous ce 1 , ce 2 , ce 2 chip enables input synchronous oe output enab le input asynchronous r/ w read/write signal input synchronous cen clock enable input synchronous bw 1 , bw 2 , bw 3 , bw 4 individ ual byte write sele cts input synchronous clk clock input n/a adv/ ld advance burst address/load new address input synchronous lbo linear/interleave d burst orde r input static zz sleep mode input asynchronous i/ o 0 -i/o 31 , i/o p1 -i/o p4 data input/output i/ o synchronous v dd , v ddq co re po we r, i/ o p owe r supply static v ss ground supply static 5315 tbl 01 IDT71V65702 idt71v65902 256k x 36, 512k x 18 3.3v synchronous zbt? srams 2.5v i/o, burst counter flow-through outputs zbt and zero bus turnaround are trademarks of integrated device technology, inc. and the architecture is supported by micron te chnology and motorola, inc. occurs, be it read or write. the IDT71V65702/5902 contain address, data-in and control signal registers. the outputs are flow-through (no output data register). output enable is the only asynchronous signal and can be used to disable the outputs at any given time. a clock enable ( cen ) pin allows operation of the IDT71V65702/5902 to be suspended as long as necessary. all synchronous inputs are ignored when cen is high and the internal device registers will hold their previous values. there are three chip enable pins ( ce 1 , ce 2 , ce 2 ) that allow the user to deselect the device when desired. if any one of these three is not asserted when adv/ ld is low, no new memory operation can be initiated. however, any pending data transfers (reads or writes) will be completed. the data bus will tri-state one cycle after the chip is deselected or a write is initiated. the IDT71V65702/5902 have an on-chip burst counter. in the burst mode, the IDT71V65702/5902 can provide four cycles of data for a single address presented to the sram. the order of the burst sequence is defined by the lbo input pin. the lbo pin selects between linear and interleaved burst sequence. the adv/ ld signal is used to load a new external address (adv/ ld = low) or increment the internal burst counter (adv/ ld = high). the IDT71V65702/5902 srams utilize idts latest high-performance cmos process, and are packaged in a jedec standard 14mm x 20mm 100-pin plastic thin quad flatpack (tqfp) as well as a 119 ball grid array (bga) and 165 fine pitch ball grid array (fbga).
6.42 2 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range symbol pin function i/o active description a 0 -a 18 address inputs i n/a synchronous address inputs. the address register is triggered by a combination of the rising edge of clk, adv/ ld low, cen low, and true chip enables. adv/ ld advance / load i n/a adv/ ld is a synchronous input that is used to load the internal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. when adv/ ld is low with the chip deselected, any burst in progress is terminated. when adv/ ld is sampled high then the internal burst counter is advanced for any burst that was in progress. the external addresses are ignored when adv/ ld is sampled high. r/ w read / write i n/a r/ w signal is a synchronous input that identifies whether the current load cycle initiated is a read or write access to the memory array. the data bus activity for the current cycle takes place one clock cycle later. cen clock enable i low synchronous clock enable input. when cen is sampled high, all other synchronous inputs, including clock are ignored and outputs remain unchanged. the effect of cen sampled high on the device outputs is as if the low to high clock transition did not occur. for normal operation, cen must be sampled low at rising edge of clock. bw 1 - bw 4 individual byte write enables i low synchronous byte write enables. each 9-bit byte has its own active low byte write enable. on load write cycles (when r/ w and adv/ ld are sampled low) the appropriate byte write signal ( bw 1 - bw 4 ) must be valid. the byte write signal must also be valid on each cycle of a burst write. byte write signals are ignored when r/ w is sampled high. the appropriate byte(s) of data are written into the device one cycle later. bw 1 - bw 4 can all be tied low if always doing write to the entire 36-bit word. ce 1 , ce 2 chip enables i low synchronous active low chip enable. ce 1 and ce 2 are used with ce 2 to enable the IDT71V65702/5902 ( ce 1 or ce 2 sampled high or ce 2 sampled low) and adv/ ld low at the rising edge of clock, initiates a deselect cycle. the zbt tm has a one cycle deselect, i.e., the data bus will tri-state one clock cycle after deselect is initiated. ce 2 chip enable i high synchronous active high chip enable. ce 2 is used with ce 1 and ce 2 to enable the chip. ce 2 has inverted polarity but otherwise identical to ce 1 and ce 2 . clk clock i n/a this is the clock input to the IDT71V65702/5902. except for oe , all timing references for the device are made with respect to the rising edge of clk. i/o 0 -i/o 31 i/o p1 -i/o p4 data input/output i/o n/a data input/output (i/o) pins. the data input path is registered, triggered by the rising edge of clk. th e data output path is flow-through (no output register). lbo linear burst order i low burst order selection input. when lbo is high the interleaved burst sequence is selected. when lbo is low the linear burst sequence is selected. lbo is a static input, and it must not change during device operation. oe output enable i low asynchronous output enable. oe must be low to read data from the 71v65702/5902. when oe is high the i/o pins are in a high-impedance state. oe does not need to be actively controlled for read and write cycles. in normal operation, oe can be tied low. zz sleep mode i high asynchronous sleep mode input. zz high will gate the clk internally and power down the IDT71V65702/5902 to its lowest power consumption level. data retention is guaranteed in sleep mode. v dd power supply n/a n/a 3.3v core power supply. v ddq power supply n/a n/a 2.5v i/o supply. v ss ground n/a n/a ground. 5315 tbl 02 pin definitions (1) note: 1. all synchronous inputs must meet specified setup and hold times with respect to clk.
6.42 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range 3 functional block diagram ? 256k x 36 clk dq dq dq address a [0:17] control logic address control di do input r egister 5315 drw 01 clock data i/o [0:31], i/o p[1:4] mux sel gate o e c e 1 ,ce 2 c e 2 r/ w c e n adv/ l d b w x l b o 256kx36bit memory array ,
6.42 4 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range functional block diagram ? 512k x 18 recommended dc operating conditions note: 1. v il (min.) = C1.0v for pulse width less than t cyc /2, once per cycle. symbol parameter min. typ. max. unit v dd core supply voltage 3.135 3.3 3.465 v v ddq i/o supply voltage 2.375 2.5 2.625 v v ss ground 0 0 0 v v ih inp ut high voltage - inp uts 1.7 ____ v dd + 0.3 v v ih inp ut high voltage - i/o 1.7 ____ v ddq + 0.3 v v il inp ut low voltage -0.3 (1) ____ 0.7 v 5315 tbl 03 clk dq dq dq address a [0:18] control logic address control di do input r egister 5315 drw 01a clock data i/o [0:15], i/o p[1:2] mux sel gate o e c e 1 ,ce 2 c e 2 r/ w c e n adv/ l d b w x l b o 512k x 18 bit memory array ,
6.42 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range 5 recommended operating temperature and supply voltage pin configuration ? 256k x 36 notes: 1. pins 14 and 66 do not have to be connected directly to v ss as long as the input voltage is v il . 2. pin 16 does not have to be connected directly to v dd as long as the input voltage is > v ih . 3. pins 84 is reserved for a future 16m. 4. dnu = do not use. pins 38, 39, 42 and 43 are reserved for respective jtag pins: tms, tdi, tdo and tck. the current die revision allows these pins to be left unconnected, tied low (v ss ), or tied high (v dd ). top view 100 tqfp grade ambient temperature (1) v ss v dd v ddq commercial 0c to +70c 0v 3.3v5% 2.5v5% industrial -40c to +85c 0v 3.3v 5% 2.5v 5% 5315 tbl 05 100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 81 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 6 a 7 c e 1 c e 2 b w 4 b w 3 b w 2 b w 1 c e 2 v d d v s s c lk r / w c e n o e a d v / ld n c (3) a 17 a 8 a 9 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 d n u (4) d n u (4) d n u (4) d n u (4) lb o a 14 a 13 a 12 a 11 a 10 v d d v s s a 0 a 1 a 2 a 3 a 4 a 5 i/o 31 i/o 30 v ddq v ss i/o 29 i/o 28 i/o 27 i/o 26 v ss v ddq i/o 25 i/o 24 v ss v dd i/o 23 i/o 22 v ddq v ss i/o 21 i/o 20 i/o 19 i/o 18 v ss v ddq i/o 17 i/o 16 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/o 14 v ddq v ss i/o 13 i/o 12 i/o 11 i/o 10 v ss v ddq i/o 9 i/o 8 v ss v dd i/o 7 i/o 6 v ddq v ss i/o 5 i/o 4 i/o 3 i/o 2 v ss v ddq i/o 1 i/o 0 5315 drw 02 v ss (1) i/o 15 i/o p3 v dd (2) i/o p4 a 15 a 16 i/o p1 v ss (1) i/o p2 zz , notes: 1. during production testing, the case temperature equals the ambient temperature.
6.42 6 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range absolute maximum ratings (1) 100 tqfp capacitance (1) (t a = +25 c, f = 1.0mhz) pin configuration ? 512k x 18 notes: 1. pins 14 and 66 do not have to be connected directly to v ss as long as the input voltage is < v il . 2. pin 16 does not have to be connected directly to v dd as long as the input voltage is > v ih . 3. pin 84 is reserved for a future 16m. 4. dnu = do not use. pins 38, 39, 42 and 43 are reserved for respective jtag pins: tms, tdi, tdo and tck. the current die revision allows these pins to be left unconnected, tied low (v ss ), or tied high (v dd ). top view 100 tqfp note: 1. this parameter is guaranteed by device characterization, but not production tested. notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v dd terminals only. 3. v ddq terminals only. 4. input terminals only. 5. i/o terminals only. 6. this is a steady-state dc parameter that applies after the power supply has reached its nominal operating value. power sequencing is not necessary; however, the voltage on any input or i/o pin cannot exceed v ddq during power supply ramp up. 7. during production testing, the case temperature equal t a . symbol rating commercial & industrial unit v te rm (2) terminal voltage with respect to gnd -0.5 to +4.6 v v te rm (3,6) terminal voltage with respect to gnd -0.5 to v dd v v te rm (4,6) terminal voltage with respect to gnd -0.5 to v dd +0.5 v v te rm (5,6) terminal voltage with respect to gnd -0.5 to v ddq +0.5 v t a (7) commercial 0 to +70 o c industrial -40 to +85 o c t bias temperature under bias -55 to +125 o c t stg storage temperature -55 to +125 o c p t power dissipation 2.0 w i out dc output current 50 ma 53 15 tb l 06 symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 5 pf c i/o i/o capacitance v out = 3dv 7 pf 5315 tbl 07 10099989796959493929190 87868584838281 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 6 a 7 c e 1 c e 2 n c n c b w 2 b w 1 c e 2 v d d v s s c lk r /w c e n o e a d v /ld n c (3) a 8 a 9 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 d n u (4) d n u (4) d n u (4) d n u (4) lb o a 15 a 14 a 13 a 12 a 11 v d d v s s a 0 a 1 a 2 a 3 a 4 a 5 nc nc v ddq v ss nc i/o p2 i/o 15 i/o 14 v ss v ddq i/o 13 i/o 12 v ss v dd i/o 11 i/o 10 v ddq v ss i/o 9 i/o 8 nc nc v ss v ddq nc nc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nc v ddq v ss nc i/o p1 i/o 7 i/o 6 v ss v ddq i/o 5 i/o 4 v ss v dd i/o 3 i/o 2 v ddq v ss i/o 1 i/o 0 nc nc v ss v ddq nc nc 5315 drw 02a v ss (1) nc nc v dd (2) nc a 16 a 17 nc v ss (1) a 10 zz a 18 , 119 bga capacitance (1) (t a = +25 c, f = 1.0mhz) symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 7 pf c i/o i/o capacitance v out = 3dv 7 pf 5315 tbl 07a symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv tbd pf c i/o i/o capacitance v out = 3dv tbd pf 5315 tb l 07b 165 fbga capacitance (1) (t a = +25 c, f = 1.0mhz)
6.42 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range 7 1234567 a v ddq a 6 a 4 a 8 a 16 v ddq b nc ce 2 a 3 adv/ ld a 9 ce 2 nc c a 7 a 2 v dd a 12 a 15 nc d i/o 16 i/o p3 v ss nc v ss i/o p2 i/o 15 e i/o 17 i/o 18 v ss v ss i/o 13 i/o 14 f v ddq i/o 19 v ss oe v ss i/o 12 v ddq g i/o 20 i/o 21 bw 3 bw 2 i/o 11 i/o 10 h i/o 22 i/o 23 v ss r/ w v ss i/o 9 i/o 8 j v ddq v dd v dd v dd v ddq k i/o 24 i/o 26 v ss clk v ss i/o 6 i/o 7 l i/o 25 i/o 27 bw 4 nc bw 1 i/o 4 i/o 5 m v ddq i/o 28 v ss cen v ss i/o 3 v ddq n i/o 29 i/o 30 v ss a 1 v ss i/o 2 i/o 1 p i/o 31 i/o p4 v ss a 0 v ss i/o 0 i/o p1 r nc a 5 lbo v dd a 13 t nc nc a 10 a 11 a 14 nc zz u v ddq dnu (4) dnu (4) dnu (4) dnu (4) dnu (4) v ddq 5315 drw 13a v ss(1) nc nc(3) ce 1 a 17 v dd(2) v ss(1) , nc 1234567 a v ddq a 6 a 4 nc(3) a 8 a 16 v ddq b nc ce2 a 3 adv/ ld a 9 ce 2 nc c a 7 a 2 v dd a 13 a 17 nc d i/o 8 nc v ss nc v ss i/o p1 nc e nc i/o 9 v ss v ss nc i/o 7 f v ddq nc v ss oe v ss i/o 6 v ddq g nc i/o 10 bw 2 nc i/o 5 h i/o 11 nc v ss r/ w v ss i/o 4 nc j v ddq v dd v dd v dd v ddq k nc i/o 12 v ss clk v ss nc i/o 3 l i/o 13 nc nc bw 1 i/o 2 nc m v ddq i/o 14 v ss cen v ss nc v ddq n i/o 15 nc v ss a 1 v ss i/o 1 nc p nc i/o p2 v ss a 0 v ss i/o 0 r nc a 5 lbo v dd a 12 t nc a 10 a 15 nc a 14 a 11 zz u v ddq dnu (4) dnu (4) dnu (4) dnu (4) v ddq 5315 drw 13b nc ss(1) v v ss v ss ce 1 a 18 v dd(2) v ss(1) , nc nc dnu (4) pin configuration ? 256k x 36, 119 bga pin configuration ? 512k x 18, 119 bga top view top view notes: 1. r5 and j5 do not have to be directly connected to v ss as long as the input voltage is < v il. 2. j3 does not have to be connected directly to v dd as long as the input voltage is 3 v ih . 3. a4 is reserved for future 16m. 4. dnu = do not use; pin u2, u3, u4, u5 and u6 are reserved for respective jtag pins: tms, tdi, tck, tdo and trst . the current die revision allows these pins to be left unconnected, tied low (v ss ), or tied high (v dd ).
6.42 8 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range pin configuration ? 256k x 36, 165 fbga pin configuration ? 512k x 18, 165 fbga notes: 1. pins h1 and n7 do not have to be directly connected to v ss as long as the input voltage is < v il. 2. pin h2 does not have to be connected directly to v dd as long as the input voltage is 3 v ih . 3. pins b9, b11, a1, r2 and p2 are reserved for future 18m, 36m, 72m, 144 and 288m respectively. 4. dnu = do not use. pins p5, r5, p7, r7 and n5 are reserved for respective jtag pins: tdi, tms, tdo, tck and trst on future revisions. the current die revision allows these pins to be left unconnected, tied low (v ss ), or tied high (v dd ). 1234567891011 anc (3) a 7 ce 1 bw 3 bw 2 ce 2 cen adv /ld a 17 a 8 nc bnc a 6 ce 2 bw 4 bw 1 clk r/ w oe nc (3) a 9 nc (3) ci/o p3 nc v ddq v ss v ss v ss v ss v ss v ddq nc i/o p2 di/o 17 i/o 16 v ddq v dd v ss v ss v ss v dd v ddq i/o 15 i/o 14 ei/o 19 i/o 18 v ddq v dd v ss v ss v ss v dd v ddq i/o 13 i/o 12 fi/o 21 i/o 20 v ddq v dd v ss v ss v ss v dd v ddq i/o 11 i/o 10 gi/o 23 i/o 22 v ddq v dd v ss v ss v ss v dd v ddq i/o 9 i/o 8 hv ss (1) v dd (2) nc v dd v ss v ss v ss v dd nc nc zz ji/o 25 i/o 24 v ddq v dd v ss v ss v ss v dd v ddq i/o 7 i/o 6 ki/o 27 i/o 26 v ddq v dd v ss v ss v ss v dd v ddq i/o 5 i/o 4 li/o 29 i/o 28 v ddq v dd v ss v ss v ss v dd v ddq i/o 3 i/o 2 mi/o 31 i/o 30 v ddq v dd v ss v ss v ss v dd v ddq i/o 1 i/o 0 ni/o p4 nc v ddq v ss dnu (3) nc v ss (1) v ss v ddq nc i/o p1 pncnc (3) a 5 a 2 dnu (3) a 1 dnu (4) a 10 a 13 a 14 nc r lbo nc (3) a 4 a 3 dnu (4) a 0 dnu (4) a 11 a 12 a 15 a 16 5315 tbl 25a 1234567891011 anc (3) a 7 ce 1 bw 2 nc ce 2 cen adv /ld a 18 a 8 a 10 bnc a 6 ce 2 nc bw 1 clk r/ w oe nc (3) a 9 nc (3) cnc ncv ddq v ss v ss v ss v ss v ss v ddq nc i/o p1 dnc i/o 8 v ddq v dd v ss v ss v ss v dd v ddq nc i/o 7 enc i/o 9 v ddq v dd v ss v ss v ss v dd v ddq nc i/o 6 fnc i/o 10 v ddq v dd v ss v ss v ss v dd v ddq nc i/o 5 gnc i/o 11 v ddq v dd v ss v ss v ss v dd v ddq nc i/o 4 hv ss (1) v dd (2) nc v dd v ss v ss v ss v dd nc nc zz ji/o 12 nc v ddq v dd v ss v ss v ss v dd v ddq i/o 3 nc ki/o 13 nc v ddq v dd v ss v ss v ss v dd v ddq i/o 2 nc li/o 14 nc v ddq v dd v ss v ss v ss v dd v ddq i/o 1 nc mi/o 15 nc v ddq v dd v ss v ss v ss v dd v ddq i/o 0 nc ni/o p2 nc v ddq v ss dnu (4) nc v ss (1) v ss v ddq nc nc pnc nc (3) a 5 a 2 dnu (4) a 1 dnu (4) a 11 a 14 a 15 nc r lbo nc (3) a 4 a 3 dnu (4) a 0 dnu (4) a 12 a 13 a 16 a 17 5315 tbl25b
6.42 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range 9 interleaved burst sequence table ( lbo =v dd ) partial truth table for writes (1) synchronous truth table (1) notes: 1. l = v il , h = v ih , x = dont care. 2. when adv/ ld signal is sampled high, the internal burst counter is incremented. the r/ w signal is ignored when the counter is advanced. therefore the nature of the burst cycle (read or write) is determined by the status of the r/ w signal when the first address is loaded at the beginning of the burst cycle. 3. deselect cycle is initiated when either ( ce 1 , or ce 2 is sampled high or ce 2 is sampled low) and adv/ ld is sampled low at rising edge of clock. the data bus will tri-state one cycle after deselect is initiated. 4. when cen is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. the state of all th e internal registers and the i/os remains unchanged. 5. to select the chip requires ce 1 = l, ce 2 = l and ce 2 = h on these chip enable pins. the chip is deselected if any one of the chip enables is false. 6. device outputs are ensured to be in high-z during device power-up. 7. q - data read from the device, d - data written to the device. notes: 1. l = v il , h = v ih , x = dont care. 2. multiple bytes may be selected during the same cycle. 3. n/a for x18 configuration. note: 1. upon completion of the burst sequence the counter wraps around to its initial state and continues counting. cen r/ w ce 1 , ce 2 (5 ) adv/ ld bw x address used previous cycle current cycle i/o (one cycle later) l l l l valid external x load write d (7 ) l h l l x external x load read q (7 ) l x x h valid internal load write / burst write burst write (advance burst counter) (2 ) d (7 ) l x x h x internal load read / burst read burst read (advance burst counter) (2 ) q (7 ) l x h l x x x deselect or stop (3 ) hiz l x x h x x deselect / noop noop hiz h x x x x x x suspend (4 ) previous value 5315 tbl 08 operation r/ w bw 1 bw 2 bw 3 (3 ) bw 4 (3 ) read hxxxx write all bytes lllll write byte 1 (i/o[0:7], i/o p1 ) (2 ) l l hhh write byte 2 (i/o[8:15], i/o p2 ) (2 ) lhlhh write byte 3 (i/o[16:23], i/o p3 ) (2,3) lhhlh write byte 4 (i/o[24:31], i/o p4 ) (2,3) l hhhl no write l hhhh 5315 tbl 09 sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address 0 0 0 1 1 0 1 1 second address 0 1 0 0 1 1 1 0 third address 1 0 1 1 0 0 0 1 fourth address (1 ) 11100 100 5315 tbl 10
6.42 10 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range functional timing diagram (1) linear burst sequence table ( lbo =v ss ) note: 1. upon completion of the burst sequence the counter wraps around to its initial state and continues counting. notes: 1. this assumes cen , ce 1 , ce 2 and ce 2 are all true. 2. all address, control and data_in are only required to meet set-up and hold time with respect to the rising edge of clock. dat a_out is valid after a clock-to-data delay from the rising edge of clock. sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address 0 0 0 1 1 0 1 1 second address 0 1 1 0 1 1 0 0 third address 1 0 1 1 0 0 0 1 fourth address (1 ) 11000 110 5315 tbl 11 n+29 a29 c29 d/q28 address (a 0 -a 17 ) control (r/ w ,adv/ ld , bw x) data i/o [0:31], i/o p[1:4] cycle clock n+30 a30 c30 d/q29 n+31 a31 c31 d/q30 n+32 a32 c32 d/q31 n+33 a33 c33 d/q32 n+34 a34 c34 d/q33 n+35 a35 c35 d/q34 n+36 a36 c36 d/q35 n+37 a37 c37 d/q36 5315 drw 03 (2) (2) (2) ,
6.42 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range 11 notes: 1. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. 2. h = high; l = low; x = don't care; z = high impedence. device operation - showing mixed load, burst, deselect and noop cycles (2) cycle address r/ w adv/ ld ce 1 (1 ) cen bw x oe i/o comments na 0 hl llxxd 1 load read n+1 x x h xlxlq 0 burst read n+2 a 1 hl llxlq 0+1 load read n+3 x x l h l x l q 1 deselect or stop n+4 x x h x l x x z noop n+5 a 2 h l l l x x z load read n+6 x x h xlxlq 2 burst read n+7 x x l h l x l q 2+1 deselect or stop n+8 a 3 l l lllxzload write n+9 x x h x l l x d 3 burst write n+10 a 4 l l lllxd 3+1 load write n+11 x x l h l x x d 4 deselect or stop n+12 x x h x l x x z noop n+13 a 5 l l lllxzload write n+14 a 6 hl llxxd 5 load read n+15 a 7 l l llllq 6 load write n+16 x x h x l l x d 7 burst write n+17 a 8 hl llxxd 7+1 load read n+18 x x h x l x l q 8 burst read n+19 a 9 l l llllq 8+1 load write 5315 tbl 12
6.42 12 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range read operation (1) burst write operation (1) burst read operation (1) write operation (1) notes: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. notes: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. notes: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. notes: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. cycle address r/ w adv/ ld ce 1 (2 ) cen bw x oe i/o comments na 0 h l l l x x x address and control meet setup n+1 x x x xxxlq 0 contents of address a 0 read out 5315 tbl 13 cycle address r/ w adv/ ld ce 1 (2 ) cen bw x oe i/o comments na 0 h l l l x x x address and control meet setup n+1 x x h xlxlq 0 address a 0 read out, inc. count n+2 x x h xlxlq 0+1 address a 0+1 read out, inc. count n+3 x x h xlxlq 0+2 address a 0+2 read out, inc. count n+4 x x h xlxlq 0+3 address a 0+3 read out, load a 1 n+5 a 1 hl llxlq 0 address a 0 read out, inc. count n+6 x x h xlxlq 1 address a 1 read out, inc. count n+7 a 2 hl llxlq 1+1 address a 1+1 read out, load a 2 5315 tbl 14 cycle address r/ w adv/ ld ce 1 (2 ) cen bw x oe i/o comments na 0 l l l l l x x address and control meet setup n+1 x x x x l x x d 0 write to address a 0 5315 tbl 15 cycle address r/ w adv/ ld ce 1 (2 ) cen bw x oe i/o comments na 0 l l l l l x x address and control meet setup n+1 x x h x l l x d 0 address a 0 write, inc. count n+2 x x h x l l x d 0+1 address a 0+1 write, inc. count n+3 x x h x l l x d 0+2 address a 0+2 write, inc. count n+4 x x h x l l x d 0+3 address a 0+3 write, load a 1 n+5 a 1 l l lllxd 0 address a 0 write, inc. count n+6 x x h x l l x d 1 address a 1 write, inc. count n+7 a 2 l l lllxd 1+1 address a 1+1 write, load a 2 5315 tbl 16
6.42 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range 13 read operation with clock enable used (1) write operation with clock enable used (1) notes: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. notes: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. cycle address r/ w adv/ ld ce 1 (2 ) cen bw x oe i/o comments na 0 h l l l x x x addressa 0 and control meet setup n+1 x x x x h x x x clock n+1 ignored n+2 a 1 hl llxlq 0 address a 0 read out, load a 1 n+3 x x x x h x l q 0 clock ignored. data q 0 is on the bus. n+4 x x x x h x l q 0 clock ignored. data q 0 is on the bus. n+5 a 2 hl llxlq 1 address a 1 read out, load a 2 n+6 a 3 hl llxlq 2 address a 2 read out, load a 3 n+7 a 4 hl llxlq 3 address a 3 read out, load a 4 5315 tbl 17 cycle address r/ w adv/ ld ce 1 (2 ) cen bw x oe i/o comments na 0 l l l l l x x address a 0 and control meet setup. n+1 x x x x h x x x clock n+1 ignored. n+2 a 1 l l lllxd 0 write data d 0 , load a 1 . n+3 x x x x h x x x clock ignored. n+4 x x x x h x x x clock ignored. n+5 a 2 l l lllxd 1 write data d 1 , load a 2 n+6 a 3 l l lllxd 2 write data d 2 , load a 3 n+7 a 4 l l lllxd 3 write data d 3 , load a 4 5315 tbl 18
6.42 14 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range read operation with chip enable used (1) write operation with chip enable used (1) notes: 1. h = high; l = low; x = dont care; ? = dont know; z = high impedance. 2. ce 2 timing transition is identical to ce 1 signal. ce 2 timing transition is identical but inverted to the ce 1 and ce 2 signals. 3. device outputs are ensured to be in high-z during device power-up. notes: 1. h = high; l = low; x = dont care; ? = dont know; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. cycle address r/ w adv/ ld ce 1 (2 ) cen bw x oe i/o (3 ) comments n x x l h l x x ? deselected. n+1 x x l h l x x z deselected. n+2 a 0 h l l l x x z address a 0 and control meet setup. n+3 x x l h l x l q 0 address a 0 read out, deselected. n+4 a 1 h l l l x x z address a 1 and control meet setup. n+5 x x l h l x l q 1 address a 1 read out, deselected. n+6 x x l h l x x z deselected. n+7 a 2 h l l l x x z address a 2 and control meet setup. n+8 x x l h l x l q 2 address a 2 read out, deselected. n+9 x x l h l x x z deselected. 5315 tbl 19 cycle address r/ w adv /ld ce (2 ) cen bw x oe i/o comments n x x l h l x x ? deselected. n+1 x x l h l x x z deselected. n+2 a 0 l l l l l x z address a 0 and control meet setup n+3 x x l h l x x d 0 data d 0 write in, deselected. n+4 a 1 l l l l l x z address a 1 and control meet setup n+5 x x l h l x x d 1 data d 1 write in, deselected. n+6 x x l h l x x z deselected. n+7 a 2 l l l l l x z address a 2 and control meet setup n+8 x x l h l x x d 2 data d 2 write in, deselected. n+9 x x l h l x x z deselected. 5315 tbl 20
6.42 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range 15 dc electrical characteristics over the operating temperature and supply voltage range (v dd = 3.3v5%) figure 2. lumped capacitive load, typical derating figure 1. ac test load ac test load ac test conditions dc electrical characteristics over the operating temperature and supply voltage range (1) (v dd = 3.3v5%) note: 1. the lbo pin will be internally pulled to v dd if it is not actively driven in the application and the zz pin will be internally pulled to v ss if not actively driven. notes: 1. all values are maximum guaranteed values. 2. at f = f max, inputs are cycling at the maximum frequency of read cycles of 1/t cyc ; f=0 means no input lines are changing. 3. for i/os v hd = v ddq C 0.2v, v ld = 0.2v. for other inputs v hd = v dd C 0.2v, v ld = 0.2v. symbol parameter test conditions min. max. unit |i l i | input leakage current v dd = max., v in = 0v to v dd ___ 5a |i li | lbo input leakage current (1 ) v dd = max., v in = 0v to v dd ___ 30 a |i lo | output leakage current v out = 0v to v cc ___ 5a v ol output low voltage i ol = +6ma, v dd = min. ___ 0.4 v v oh output high voltage i oh = -6ma, v dd = min. 2.0 ___ v 5001 tbl 21 symbol parameter test condi tions 7.5ns 8ns 8.5ns unit com'l ind com'l ind com'l ind i dd operating power supply current device selected, outputs open, adv/ ld = x, v dd = max., v in > v ih or < v il , f = f max (2) 275 295 250 270 225 245 ma i sb1 cmos standby power supply current device deselected, outputs open, v dd = max., v in > v hd or < v ld , f = 0 (2,3) 40 60 40 60 40 60 ma i sb2 clock running po we r supply current device deselected, outputs open, v dd = max., v in > v hd or < v ld , f = f max (2,3) 105 125 100 120 95 115 ma i sb3 id le po we r supply current device selected, outputs open, cen > v ih , v dd = max., v in > v hd or < v ld , f = f max (2,3) 40 60 40 60 40 60 ma i zz full sleep mode supply current device selected, outputs open cen v il , v dd = max., zz 3 v hd v in 3 v hd or v ld , f = f max (2, 3) 40 60 40 60 40 60 ma 5315 tbl 22 input pulse levels input rise/fall times input timing reference levels output reference levels output load 0 to 2.5v 2ns v dd q / 2 v dd q / 2 figure 1 5315 tbl 23 v ddq /2 50 w i/o z 0 =50 w 5315 drw 04 , 1 2 3 4 20 30 50 100 200 d t cd (typical, ns) capacitance (pf) 80 5 6 5315 drw 05 ,
6.42 16 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range ac electrical characteristics (v dd = 3.3v5%, commercial and industrial temperature ranges) notes: 1. measured as high above 0.6v ddq and low below 0.4v ddq . 2. transition is measured 200mv from steady-state. 3. these parameters are guaranteed with the ac load (figure 1) by device characterization. they are not production tested. 4. to avoid bus contention, the output buffers are designed such that t chz (device turn-off) is about 1ns faster than t clz (device turn-on) at a given temperature and voltage. the specs as shown do not imply bus contention because t clz is a min. parameter that is worse case at totally different test conditions (0 deg. c, 3.465v) than t chz , which is a max. parameter (worse case at 70 deg. c, 3.135v). 7.5ns 8ns 8.5ns symbol parameter min. max. min. max. min. max. unit t cy c clock cycle time 10 ____ 10.5 ____ 11 ____ ns t ch (1 ) clock high pulse width 2.5 ____ 2.7 ____ 3.0 ____ ns t cl (1 ) clock low pulse width 2.5 ____ 2.7 ____ 3.0 ____ ns output parameters t cd clock high to valid data ____ 7.5 ____ 8 ____ 8.5 ns t cd c clock high to data change 2 ____ 2 ____ 2 ____ ns t cl z (2 , 3 ,4 ) clock high to output active 3 ____ 3 ____ 3 ____ ns t chz (2 , 3 ,4 ) clock high to data high-z ____ 5 ____ 5 ____ 5ns t oe output enable access time ____ 5 ____ 5 ____ 5ns t olz (2,3) output enable low to data active 0 ____ 0 ____ 0 ____ ns t ohz (2,3) output enable high to data high-z ____ 5 ____ 5 ____ 5ns set up times t se clock enable setup time 2.0 ____ 2.0 ____ 2.0 ____ ns t sa address setup time 2.0 ____ 2.0 ____ 2.0 ____ ns t sd data in setup time 2.0 ____ 2.0 ____ 2.0 ____ ns t sw read/write (r/ w ) setup time 2.0 ____ 2.0 ____ 2.0 ____ ns t sadv advance/load (adv/ ld ) setup time 2.0 ____ 2.0 ____ 2.0 ____ ns t sc chip enable/select setup time 2.0 ____ 2.0 ____ 2.0 ____ ns t sb byte write enable ( bw x) setup time 2.0 ____ 2.0 ____ 2.0 ____ ns hold times t he clock enable hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t ha address hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hd data in hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hw read/write (r/ w ) hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hadv advance/load (adv/ ld ) hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hc chip enable/select hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hb byte write enable ( bw x) hold time 0.5 ____ 0.5 ____ 0.5 ____ ns 5315 tbl 24
6.42 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range 17 timing waveform of read cycle (1,2,3,4) notes: 1. q (a 1 ) represents the first output from the external address a 1 . q (a 2 ) represents the first output from the external address a 2 ; q (a 2+1 ) represents the next output data in the burst sequence of the base address a 2 , etc. where address bits a 0 and a 1 are advancing for the four word burst in the sequence defined by the state of the lbo input. 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. burst ends when new address and control are loaded into the sram by sampling adv/ ld low. 4. r/ w is dont care when the sram is bursting (adv/ ld sampled high). the nature of the burst access (read or write) is fixed by the state of the r/ w signal when new address and control are loaded into the sram. ( c e n high, elim inates current l-h clock edge) q (a 2+1 ) t c d r ead t c lz t c h z t c d t c d c q (a 2+2 ) q (a 1 ) q (a 2 ) q (a 2+3 ) q (a 2+3 ) q (a 2 ) b urst r ead r ead d a t a o u t (b urst w raps around to initial state) t c d c t h a d v 531 5 drw 06 r / w c lk a d v / ld a d d r e s s c e 1 , c e 2 (2) b w 1 - b w 4 o e t h e t s e a 1 a 2 t c h t c l t c y c t s a d v t h w t s w t h a t s a t h c t s c c e n ,
6.42 18 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range timing waveform of write cycles (1,2,3,4,5) notes: 1. d (a 1 ) represents the first input to the external address a 1 . d (a 2 ) represents the first input to the external address a 2 ; d (a 2+1 ) represents the next input data in the burst sequence of the base address a 2 , etc. where address bits a 0 and a 1 are advancing for the four word burst in the sequence defined by the state of the lbo input. 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. burst ends when new address and control are loaded into the sram by sampling adv/ ld low. 4. r/ w is dont care when the sram is bursting (adv/ ld sampled high). the nature of the burst access (read or write) is fixed by the state of the r/ w signal when new address and control are loaded into the sram. 5. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in one cycle before the actual data is presented to the sram. t h e t s e r / w a 1 a 2 c l k c e n a d v / l d a d d r e s s c e 1 , c e 2 (2) b w 1 - b w 4 o e d a ta in d (a 1 ) d (a 2 ) t h d t s d ( c e n high, elim inates current l-h clock edge) d (a 2+1 ) d (a 2+ 2 ) d (a 2+3 ) d (a 2 ) b urst w rite w rite w rite (b urst w raps around to initial state) t h d t s d t c h t c l t c y c t h a d v t s a d v t h w t s w t h a t s a t h c t s c t h b t s b 531 5 drw 07 b (a 1 ) b (a 2 ) b (a 2+ 1 ) b (a 2+ 2 ) b (a 2+3 ) b (a 2 ) ,
6.42 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range 19 timing waveform of combined read and write cycles (1,2,3) notes: 1. q (a 1 ) represents the first output from the external address a 1 . d (a 2 ) represents the input data to the sram corresponding to address a 2 . 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in one cycle before the actual data is presented to the sram. t h e t s e r / w a 1 a 2 c lk c e n a d v / ld a d d r e s s c e 1 , c e 2 (2) b w 1 - b w 4 d a t a o u t q (a 3 ) q (a 1 ) q (a 6 ) q (a 7 ) t c d r ead r ead r ead r ead t c h z 5315 drw 08 w rite t c lz d (a 2 ) d (a 4 ) t c d c d (a 5 ) w rite t c h t c l t c y c t h w t s w t h a t s a a 4 a 3 t h c t s c t s d t h d t h a d v t s a d v a 6 a 7 a 8 a 5 a 9 d a t a in t h b t s b w rite d (a 8 ) w rite b (a 2) b (a 4 ) b (a 5 ) b (a 8 ) o e ,
6.42 20 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range timing waveform of cen operation (1,2,3,4) notes: 1. q (a 1 ) represents the first output from the external address a 1 . d (a 2 ) represents the input data to the sram corresponding to address a 2 . 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. cen when sampled high on the rising edge of clock will block that l-h transition of the clock from propogating into the sram. the part will behave as if the l-h clock transition did not occur. all internal registers in the sram will retain their previous state. 4. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in one cycle before the actual data is presented to the sram. t h e t s e r / w a 1 a 2 c l k c e n a d v / l d a d d r e s s c e 1 , c e 2 (2) b w 1 - b w 4 o e d a t a o u t q (a 1 ) t c d c q (a 3 ) t c d t c lz q (a 1 ) q (a 4 ) t c d t c d c t c h z d (a 2 ) t s d t h d t c h t c l t c y c t h c t s c a 4 a 5 t h a d v t s a d v t h w t s w t h a t s a a 3 t h b t s b d a t a in 5315 drw 09 b (a 2 ) ,
6.42 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range 21 timing waveform of cs operation (1,2,3,4) notes: 1. q (a 1 ) represents the first output from the external address a 1 . d (a 3 ) represents the input data to the sram corresponding to address a 3 etc. 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. when either one of the chip enables ( ce 1 , ce2, ce 2 ) is sampled inactive at the rising clock edge, a deselect cycle is initiated. the data-bus tri-states one cycle after the init iation of the deselect cycle. this allows for any pending data transfers (reads or writes) to be completed. 4. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in one cycle before the actual data is presented to the sram. r / w a 1 c l k a d v / l d a d d r e s s c e 1 , c e 2 (2) o e d a t a o u t q (a 1 ) q (a 2 ) q (a 4 ) t c lz q (a 5 ) t c d t c h z t c d c d (a 3 ) t s d t h d t c h t c l t c y c t h c t s c a 5 a 3 t s b d a t a in t h e t s e a 2 t h a t s a a 4 t h w t s w t h b c e n t h a d v t s a d v 5315 drw 10 b w 1 - b w 4 b (a 3 ) , ,
6.42 22 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range 100-pin thin quad plastic flatpack (tqfp) package diagram outline
6.42 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range 23 119 ball grid array (bga) package diagram outline
6.42 24 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range 165 fine pitch ball grid array (fbga) package diagram outline
6.42 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range 25 timing waveform of oe operation (1) note: 1. a read operation is assumed to be in progress. ordering information oe data out t ohz t olz t oe q 5315 drw 11 q , 100-pin plastic thin quad flatpack (tqfp) 119 ball grid array (bga) 165 fine pitch ball grid array (fbga) s power xx speed xx package pf bg bq idt xxxx 75 80 85 access time (t cd ) in tenths of nanoseconds 5315 drw 12 device type IDT71V65702 idt71v65902 256kx36 flow-through zbt sram 512kx18 flow-through zbt sram , blank i xx process/temp range commercial (0c to +70c) industrial (-40c to +85c)
6.42 26 IDT71V65702, idt71v65902, 256k x 36, 512k x 18, 3.3v synchronous zbt? srams with 3.3v or 2.5v i/o, burst counter, and flow-through outputs commercial and industrial temperature range corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 sramhelp@idt.com santa clara, ca 95054 fax: 408-492-8674 800-544-7726 www.idt.com the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 12/31/99 created new datasheet from obsolete devices idt71v657 and idt71v659 04/20/00 pg.5,6 added jtag test pins to tqfp pin configuration; removed footnote add clarification note to recommended operating temperatures and absolute maxrating table pg. 7 add note to bga pin configuration; corrected typo within pinout pg. 21 insert tqfp package diagram outline 05/23/00 added new package offering: 13mm x 15mm, 165 fbga pg. 23 correction on 119 bga package diagram outline 07/28/00 pg. 5-8 remove jtag pins from tqfp, bg119 and bq165 pinouts refer to idt71v656xx and idt71v658xx device errata sheet pg. 7,8 correct error in pinout, b2 on bg119 and b1 on bq165 pinout pg. 23 update bg119 package diagram dimensions 11/04/00 pg. 8 add reference note to pin n5, bq165 pinout, reserved for jtag trst pg. 15 add izz to dc electrical characteristics 08/08/02 pg. 5,6,15,16,25 added industrial information to datasheet. 12/04/02 pg. 1-26 changed datasheet from prelininary to final release. pg. 6 corrected absolute max. table (added i temp to heading in table) 12/18/02 pg. 1,2,5,6,7,8 removed jtag functionality for current die revision. pg. 7 corrected pin configuration x36,119bga. switched i/o0 and i/op1. 10/15/04 pg. 5& 6 updated temperature ta note. pg. 7 updated pin configuration 512k x 18 for the 119 bga - reordered i/o signals on p7, n6, l6, k7, h6, g7, f6, e7, d6.

▲Up To Search▲

Price & Availability of IDT71V65702

	To Download IDT71V65702 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .